FPGA Ch1_4

أعزائى القراء المحترمين 

السلام عليكم ورحمة الله وبركاته 

 أقدم لكم اليوم المدونة الرابعة في الفصل الأول عن مصفوفة البوابات المنطقية القابلة للبرمجة في مجال العمل 

(Field  Programmable Gate Array  FPGA ).

Chapter 1

1.5 FPGA

       FPGA is an abbreviation for Field Programmable Gate Array. It is a sub-group to Application Specific Integrated Circuits, ASIC. ASICs are designed at transistor-level. The transistors with connections are made by a design-process involving building layers using e.g. diffusion. A simplification of this is using standard-cells. These are e.g. adders or other functions that are connected to produce the function desired. There are other design-processes but they will not be described here. What ASICs and the different design-processes of these have in common is that once produced, they can’t be changed. An FPGA is a gate- matrix in which the connections between and within the cells are programmed. An FPGA then gains the same benefits as an ASIC but the silicon used is larger in the FPGA than in the ASIC. This means the area of silicon isn’t optimized and the speed of the FPGA is slower than for an ASIC. Another solution to design problems is to use standard-circuits and microprocessors. These are cheap since they are produced in large series. They can be programmed by using a high-definition language, e.g. C. It makes it easy to change or create new code. An FPGA share both the ASIC and the microprocessor’s benefits. It can be used to fast design application-specific designs and the circuits programmed can easily be changed on the circuit board with a newly programmed FPGA. The drawback is the cost of the FPGA compared to an ASIC in large quantities. The FPGA functions can be programmed at different levels. One can go directly inside the cells or use higher-level components such as e.g. NAND, adders, registers, flip- flops and more. There are several manufacturers of FPGA. Actel are one, Xilinx another.

1.5.1 VHDL

       VHDL is an abbreviation of Very high-speed integrated circuit Hardware Description Language. It is a standardized language used to specify, verify, and design electronics. VHDL was developed by the US department of defense at the beginning of the eighties and was made a standard for

modeling and simulating. The translation of VHDL-code to a net- list for e.g. an FPGA is called synthesis. The synthesizing process is not made into a standard thus it is the synthesizer tool that decides what VHDL-code constructs that are supported for synthesis. VHDL is an object-based language. It is a big and general hardware-descriptive language, which gives several opportunities to describe the same behavior with different language-designs. The design itself is made up of components consisting of two parts. Entity In and output signals of the component Architecture Behavior of the entity, described by different abstraction models. The component can be described by different abstraction- levels and structural descriptions. The abstraction- levels can describe the same function but with different levels of detail.

       When using VHDL it is possible to mix different abstraction-levels simply by connecting the different components that are using different levels. The different levels used in practical electronic design are:

The Behavior-model.

RTL-Model (Register Transfer Level).

Gate- level.

         

       The behavior model is used at an early stage as a specification on how the circuit is supposed to work, thus it is easy to read and can also be used for documentation. The RTL- model describes the behavior in asynchrone and synchrone state-machines, bus-structures, operators, registers, multiplexers, ALU and many more structures. These exist in different language-designs that can be synthesized if the synthesis-tool supports it.

       Gate level is the lowest abstraction level used for synthesis. At this level a gate- net is written or the design is described using Boolean algebra. This level gives the most control over synthesis and optimizing of circuit-area.

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

ENTITY fulladd IS

        PORT ( Cin, x, y : IN SID_LOGIC ;

                      s, Cout   : OUT STD_LOGIC ) ;

END fulladd ;

ARCHITECTURE LogicFunc OF fulladd IS

BEGIN

     s <= x XOR y XOR Cin ;

     Cout <= (x AND y) OR (x AND Cin) OR (y AND Cin) ;

END LogicFunc ;

Example for VHDL Code for a full _Adder

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